331 search results - page 28 / 67 » Low power implementation of a turbo-decoder on programmable ... |
173
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ARCS
2008
Springer
15 years 8 months ago
2008
Springer
: The architecture of the IBM Cell BE processor represents a new approach for designing CPUs. The fast execution of legacy software has to stand back in order to achieve very high ...
160
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ISLPED
1997
ACM
15 years 9 months ago
1997
ACM
Significand pre-alignment is a pre requisite for floating point additions. This paper1 addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch ...
163
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AHS
2006
IEEE
15 years 12 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
192
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VLSID
2007
IEEE
16 years 6 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
174
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ASPLOS
2012
ACM
14 years 1 months ago
2012
ACM
Numerous data center services exhibit low average utilization leading to poor energy efficiency. Although CPU voltage and frequency scaling historically has been an effective mea...