41 search results - page 3 / 9 » M-trie: an efficient approach to on-chip logic minimization |
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
PLILP
1994
Springer
13 years 11 months ago
1994
Springer
We present the design and the implementation of clp(B): a boolean constraint solver inside the Constraint Logic Programming paradigm. This solver is based on local propagation meth...
INFOCOM
2012
IEEE
11 years 9 months ago
2012
IEEE
Packet classification is one of the major challenges in designing high-speed routers and firewalls as it involves sophisticated multi-dimensional searching. Ternary Content Address...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
? An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for co...
ERSA
2006
13 years 8 months ago
2006
Thermal monitoring of a design plays a vital role to ensure safe and reliable thermal operating conditions. Thermal monitoring by employing thermal sensors is a popular technique ...