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IEEEPACT
2002
IEEE
14 years 2 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
ICSE
2004
IEEE-ACM
14 years 9 months ago
A Hybrid Architectural Style for Distributed Parallel Processing of Generic Data Streams
Immersive, interactive applications grouped under the concept of Immersipresence require on-line processing and mixing of multimedia data streams and structures. One critical issu...
Alexandre R. J. François
AAAIDEA
2005
IEEE
14 years 2 months ago
Design and Evaluation of Diffserv Functionalities in the MPLS Edge Router Architecture
—Differentiated Service (DiffServ) in combination with Multi-Protocol Label Switching (MPLS) is a promising technology in converting the best-effort Internet into a QoS-capable n...
Wei-Chu Lai, Kuo-Ching Wu, Ting-Chao Hou
ASAP
1997
IEEE
155views Hardware» more  ASAP 1997»
14 years 19 days ago
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a qu...
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, ...
SOCA
2010
IEEE
13 years 7 months ago
Exploiting multicores to optimize business process execution
While modern CPUs offer an increasing number of cores with shared caches, prevailing execution engines for business processes, workflows, or Web service compositions have not been ...
Achille Peternier, Daniele Bonetta, Cesare Pautass...