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FCCM
2009
IEEE
148views VLSI» more  FCCM 2009»
14 years 4 months ago
A Packet Generator on the NetFPGA Platform
— A packet generator and network traffic capture system has been implemented on the NetFPGA. The NetFPGA is an open networking platform accelerator that enables rapid developmen...
G. Adam Covington, Glen Gibb, John W. Lockwood, Ni...
ISCA
2009
IEEE
161views Hardware» more  ISCA 2009»
14 years 4 months ago
AnySP: anytime anywhere anyway signal processing
In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world—a device that we...
Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. ...
IEEEPACT
2008
IEEE
14 years 4 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 3 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
FPL
2009
Springer
107views Hardware» more  FPL 2009»
14 years 2 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...