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FPL
2004
Springer
119views Hardware» more  FPL 2004»
14 years 1 months ago
Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor
Pervasive networks with low-cost embedded 8-bit processors are set to change our day-to-day life. Public-key cryptography provides crucial functionality to assure security which is...
Sandeep S. Kumar, Christof Paar
FPL
2006
Springer
105views Hardware» more  FPL 2006»
14 years 1 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
APCCAS
2006
IEEE
261views Hardware» more  APCCAS 2006»
13 years 11 months ago
A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed Outputs
- In this paper, the grouped scheme is specially applied to compute the fast Fourier transform (FFT) when the portions of transformed outputs are calculated selectively. The groupe...
Chih-Peng Fan, Guo-An Su
ARC
2010
Springer
183views Hardware» more  ARC 2010»
13 years 10 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
JUCS
2008
140views more  JUCS 2008»
13 years 9 months ago
Parallel Formulations of Scalar Multiplication on Koblitz Curves
We present an algorithm that by using the and -1 Frobenius operators concurrently allows us to obtain a parallelized version of the classical -and-add scalar multiplication algor...
Omran Ahmadi, Darrel Hankerson, Francisco Rodr&iac...