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CAV
1998
Springer
175views Hardware» more  CAV 1998»
13 years 11 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
EON
2008
13 years 8 months ago
Debugging OWL Ontologies - A Reality Check
One of the arguments for choosing description logics as the basis for the Web Ontology Language is the ability to support the development of complex ontologies through logical reas...
Heiner Stuckenschmidt
GLVLSI
2007
IEEE
171views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Combinational equivalence checking for threshold logic circuits
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevo...
CIE
2010
Springer
14 years 4 days ago
The Peirce Translation and the Double Negation Shift
We develop applications of selection functions to proof theory and computational extraction of witnesses from proofs in classical analysis. The main novelty is a translation of cla...
Martín Hötzel Escardó, Paulo Ol...
CORR
2008
Springer
141views Education» more  CORR 2008»
13 years 7 months ago
Model checking memoryful linear-time logics over one-counter automata
We study complexity of the model-checking problems for LTL with registers (also known as freeze LTL and written LTL ) and for first-order logic with data equality tests (written F...
Stéphane Demri, Ranko Lazic, Arnaud Sangnie...