9 search results - page 1 / 2 » Maintaining Packet Order In Two-stage Switches |
TON
2010
13 years 5 months ago
2010
Abstract--A framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unl...
INFOCOM
2002
IEEE
14 years 3 months ago
2002
IEEE
-- High performance packet switches frequently use a centralized scheduler (also known as an arbiter) to determine the configuration of a non-blocking crossbar. The scheduler often...
GCC
2003
Springer
14 years 4 months ago
2003
Springer
INFOCOM
1996
IEEE
14 years 3 months ago
1996
IEEE
This report analyzes two popular heuristics for ensuring packet integrity in ATM switching systems. In particular, we analyze the behavior of packet tail discarding, in order to u...
INFOCOM
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— Network operators need high capacity router architectures that can offer scalability, provide throughput guarantees, and maintain packet ordering. However, current cent...