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CONCURRENCY
2000
106views more  CONCURRENCY 2000»
13 years 9 months ago
Performance characteristics for OpenMP constructs on different parallel computer architectures
OpenMP is emerging as a quasi-standard for shared memory parallel programming on small SMP-systems. To serve as a common programming interface in shared memory parallel programmin...
Rudolf Berrendorf, Guido Nieken
CGO
2003
IEEE
14 years 3 months ago
Optimizing Memory Accesses For Spatial Computation
In this paper we present the internal representation and optimizations used by the CASH compiler for improving the memory parallelism of pointer-based programs. CASH uses an SSA-b...
Mihai Budiu, Seth Copen Goldstein
EMSOFT
2006
Springer
14 years 1 months ago
A superblock-based flash translation layer for NAND flash memory
In NAND flash-based storage systems, an intermediate software layer called a flash translation layer (FTL) is usually employed to hide the erase-before-write characteristics of NA...
Jeong-Uk Kang, Heeseung Jo, Jinsoo Kim, Joonwon Le...
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
14 years 6 months ago
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
PARELEC
2006
IEEE
14 years 4 months ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich