Sciweavers

    55 search results - page 3 / 11
    » Mapping of DSP Algorithms on Field Programmable Function Arr...
    Sort
    View
    BMCBI
    2010
    109views more  BMCBI 2010»
    FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods
    13 years 7 months ago
    FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods
    Download  www.cse.sc.edu
    Background: Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. Th...
    Stephanie Zierke, Jason D. Bakos
    claim paper
    Read More »
    EH
    2002
    IEEE
    112views Hardware» more  EH 2002»
    Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System
    14 years 11 days ago
    Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System
    Download  ehw.jpl.nasa.gov
    The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occ...
    Adrian Stoica, Ricardo Salem Zebulum, Michael I. F...
    claim paper
    Read More »
    TCAD
    2008
    112views more  TCAD 2008»
    Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
    13 years 7 months ago
    Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
    Download  www.ece.ualberta.ca
    Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
    Yu Hu, Victor Shih, Rupak Majumdar, Lei He
    claim paper
    Read More »
    ERSA
    2009
    147views Hardware» more  ERSA 2009»
    Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
    13 years 5 months ago
    Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
    Download  eecs.wsu.edu
    Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
    Kylan Robinson, José G. Delgado-Frias
    claim paper
    Read More »
    TVLSI
    2008
    133views more  TVLSI 2008»
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    13 years 7 months ago
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    Download  www.eecs.wsu.edu
    Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
    Mitchell J. Myjak, José G. Delgado-Frias
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.