391 search results - page 53 / 79 » Massively parallel processing on a chip |
VLDB
1998
ACM
13 years 12 months ago
1998
ACM
This paper describes the external forces that motivate financial institutions to collect, aggregate, analyze, and mine data so that it can be transformed into information, one of ...
TPDS
1998
13 years 7 months ago
1998
—This paper presents a cohesive, practical load balancing framework that improves upon existing strategies. These techniques are portable to a broad range of prevalent architectu...
AHS
2006
IEEE
13 years 11 months ago
2006
IEEE
We propose a novel type of dynamically reconfigurable System-on-Chip architecture, the Gannet service-based architecture. This novel concept addresses the issue of systemlevel rec...
LCPC
2005
Springer
14 years 1 months ago
2005
Springer
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten developmen...
FPL
2009
Springer
14 years 8 days ago
2009
Springer
Networks-on-Chips (NoCs) are an emerging communication topology paradigm in single chip VLSI design, enhancing parallelism and system scalability. Processing units (PUs) connect t...