Sciweavers

462 search results - page 10 / 93
» Maximal AMDS codes
Sort
View
EUROPAR
2009
Springer
14 years 2 months ago
A Multilevel Parallelization Framework for High-Order Stencil Computations
Stencil based computation on structured grids is a common kernel to broad scientific applications. The order of stencils increases with the required precision, and it is a challeng...
Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard ...
SIPEW
2009
Springer
119views Hardware» more  SIPEW 2009»
14 years 2 months ago
A Tale of Two Processors: Revisiting the RISC-CISC Debate
The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Nowadays, processors with CISC-ISAs translate the CISC instructions i...
Ciji Isen, Lizy K. John, Eugene John
CGO
2007
IEEE
14 years 1 months ago
Rapidly Selecting Good Compiler Optimizations using Performance Counters
Applying the right compiler optimizations to a particular program can have a significant impact on program performance. Due to the non-linear interaction of compiler optimization...
John Cavazos, Grigori Fursin, Felix V. Agakov, Edw...
IPPS
2007
IEEE
14 years 1 months ago
Runtime Optimization of Application Level Communication Patterns
— This paper introduces the Abstract Data and Communication Library (ADCL). ADCL is an application level communication library aiming at providing the highest possible performanc...
Edgar Gabriel, Shuo Huang
PPL
2008
264views more  PPL 2008»
13 years 7 months ago
A Performance Evaluation of the Nehalem Quad-Core Processor for Scientific Computing
In this work we present an initial performance evaluation of Intel's latest, secondgeneration quad-core processor, Nehalem, and provide a comparison to first-generation AMD a...
Kevin J. Barker, Kei Davis, Adolfy Hoisie, Darren ...