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ICASSP
2008
IEEE
14 years 2 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
SAC
2009
ACM
14 years 2 months ago
Celling SHIM: compiling deterministic concurrency to a heterogeneous multicore
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
Nalini Vasudevan, Stephen A. Edwards
RTSS
1989
IEEE
14 years 1 days ago
A Distributed Fault Tolerant Architecture for Nuclear Reactor Control and Safety Functions
A new fault tolerant architecture that provides tolerance to a broad scope of hardware, software, and communications faults is being developed. This architecture relies on widely ...
Myron Hecht, J. Agron, S. Hochhauser
CCGRID
2005
IEEE
14 years 1 months ago
Using semantic Web technology to automate data integration in grid and Web service architectures
While the Grid and Web Services have helped us support heterogeneous resource access through the use of service oriented architectures, they have not addressed the issue of hetero...
Martin Szomszor, Terry R. Payne, Luc Moreau
IWANN
2005
Springer
14 years 1 months ago
Co-evolutionary Learning in Liquid Architectures
A large class of problems requires real-time processing of complex temporal inputs in real-time. These are difficult tasks for state-of-the-art techniques, since they require captu...
Igal Raichelgauz, Karina Odinaev, Yehoshua Y. Zeev...