1095 search results - page 144 / 219 » Measuring the Performance of Parallel Message-Based Process ... |
90
Voted
ICCAD
2005
IEEE
15 years 11 months ago
2005
IEEE
We describe an interconnect scheme based on lossy transmission lines, compare this scheme with traditional bus based links, and present performance data. Unlike some other schemes...
127
Voted
DAC
2006
ACM
16 years 3 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
121
Voted
HPCA
1999
IEEE
15 years 6 months ago
1999
IEEE
Researchers have searched for scalable alternatives to the symmetric multiprocessor (SMP) architecture since it was first introduced in 1982. This paper introduces an alternative ...
129
Voted
HPDC
2009
IEEE
15 years 9 months ago
2009
IEEE
This paper explores the feasibility of a cost-efficient storage architecture that offers the reliability and access performance characteristics of a high-end system. This architec...
132
Voted
IWMM
2000
Springer
15 years 6 months ago
2000
Springer
We investigate reference counting in the context of a multithreaded architecture by exploiting two observations: (1) reference-counting can be performed by a transformed program s...