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LCPC
2005
Springer
14 years 1 months ago
Compiler Control Power Saving Scheme for Multi Core Processors
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten developmen...
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroak...
IPPS
2003
IEEE
14 years 1 months ago
Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms
This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence...
João M. P. Cardoso
CCGRID
2005
IEEE
13 years 10 months ago
The Composite Endpoint Protocol (CEP): scalable endpoints for terabit flows
We introduce the Composite Endpoint Protocol (CEP) which efficiently composes a set of transmission elements to support high speed flows which exceed the capabilities of a single...
Eric Weigle, Andrew A. Chien
DPD
2006
98views more  DPD 2006»
13 years 8 months ago
GRACE-based joins on active storage devices
Contemporary long-term storage devices feature powerful embedded processors and sizeable memory buffers. Active Storage Devices (ASD) is the hard disk technology that makes use of ...
Vassilis Stoumpos, Alex Delis
PVM
2010
Springer
13 years 6 months ago
Implementing MPI on Windows: Comparison with Common Approaches on Unix
Commercial HPC applications are often run on clusters that use the Microsoft Windows operating system and need an MPI implementation that runs efficiently in the Windows environmen...
Jayesh Krishna, Pavan Balaji, Ewing L. Lusk, Rajee...