Sciweavers

1095 search results - page 33 / 219
» Measuring the Performance of Parallel Message-Based Process ...
Sort
View
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
14 years 6 days ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
ICASSP
2011
IEEE
12 years 11 months ago
Fast estimation of the state of the power grid using synchronized phasor measurements
—Both the communication limitation and the measurement properties based algorithm become the bottleneck of enhancing the traditional power system state estimation speed. The avai...
Tao Yang, Anjan Bose
HPCA
1998
IEEE
14 years 1 days ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
13 years 11 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
INFOCOM
2006
IEEE
14 years 1 months ago
Performance of Full Text Search in Structured and Unstructured Peer-to-Peer Systems
— While structured P2P systems (such as DHTs) are often regarded as an improvement over unstructured P2P systems (such as super-peer networks) in terms of routing efficiency, it...
Yong Yang, Rocky Dunlap, Mike Rexroad, Brian F. Co...