753 search results - page 17 / 151 » Mechanisms for Mapping High-Level Parallel Performance Data |
110
Voted
HIPS
1998
IEEE
15 years 6 months ago
1998
IEEE
Distributed shared objects are a well known approach to achieve independenceof the memory model for parallel programming. The illusion of shared (global) objects is a conabstracti...
160
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ASAP
1996
IEEE
15 years 6 months ago
1996
IEEE
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
134
Voted
ASPLOS
2009
ACM
15 years 9 months ago
2009
ACM
This paper presents a performance analysis of an accelerated 2-D rigid image registration implementation that employs the Compute Unified Device Architecture (CUDA) programming e...
128
Voted
IPPS
2000
IEEE
15 years 7 months ago
2000
IEEE
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
139
Voted
PDP
2010
IEEE
15 years 8 months ago
2010
IEEE
- We present a parallel conjugate gradient solver for the Poisson problem optimized for multi-GPU platforms. Our approach includes a novel heuristic Poisson preconditioner well sui...