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» Mechanization for solving SPP by reducing order method
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EAAI
2008
106views more  EAAI 2008»
13 years 8 months ago
The distributed multilevel ant-stigmergy algorithm used at the electric-motor design
This article presents an optimization method used at the electric-motor design. The goal of the optimization was to find the geometrical parameter values that would generate the r...
Peter Korosec, Jurij Silc
TCAD
2008
116views more  TCAD 2008»
13 years 8 months ago
Scalable Synthesis and Clustering Techniques Using Decision Diagrams
BDDs have proven to be an efficient means to represent and manipulate Boolean formulae [1] and sets [2] due to their compactness and canonicality. In this work, we leverage the eff...
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
SIGECOM
2003
ACM
107views ECommerce» more  SIGECOM 2003»
14 years 1 months ago
Using value queries in combinatorial auctions
Combinatorial auctions, where bidders can bid on bundles of items are known to be desirable auction mechanisms for selling items that are complementary and/or substitutable. Howev...
Benoît Hudson, Tuomas Sandholm
ICPP
2007
IEEE
14 years 2 months ago
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
As the number of computing and storage nodes keeps increasing, the interconnection network is becoming a key element of many computing and communication systems, where the overall...
Gaspar Mora, Pedro Javier García, Jose Flic...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...