60 search results - page 8 / 12 » Memory Estimation for High Level Synthesis |
DCC
2008
IEEE
13 years 9 months ago
2008
IEEE
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
TSD
2004
Springer
14 years 28 days ago
2004
Springer
Abstract. This paper presents a brand-new Slovak text-to-speech system. It was developed within the framework of ARTIC system (primarily designed to synthesize Czech speech) with r...
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
eously demand shorter and less costly design cycles. Designing at higher levels of abstraction makes both objectives achievable, but enabling techniques like behavioral synthesis h...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...