34 search results - page 4 / 7 » Memory Model = Instruction Reordering Store Atomicity |
JPDC
2006
2006
A tight bound on remote reference time complexity of mutual exclusion in the read-modify-write model
13 years 7 months ago
In distributed shared memory multiprocessors, remote memory references generate processor-to-memory traffic, which may result in a bottleneck. It is therefore important to design ...
POPL
2010
ACM
14 years 4 months ago
2010
ACM
We address the verification problem of finite-state concurrent programs running under weak memory models. These models capture the reordering of program (read and write) operation...
PLDI
2012
ACM
11 years 10 months ago
2012
ACM
Modern architectures implement relaxed memory models which may reorder memory operations or execute them non-atomically. Special instructions called memory fences are provided, al...
CASES
2010
ACM
13 years 5 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
HICSS
1995
IEEE
13 years 11 months ago
1995
IEEE
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...