276 search results - page 30 / 56 » Memory Organization for Improved Data Cache Performance in E... |
JTRES
2010
ACM
13 years 8 months ago
2010
ACM
In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led...
ICPPW
2002
IEEE
14 years 1 months ago
2002
IEEE
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transf...
HPCA
1999
IEEE
14 years 24 days ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
CASES
2006
ACM
14 years 2 months ago
2006
ACM
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
VLDB
1999
ACM
14 years 22 days ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...