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MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
14 years 13 days ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
ICS
1998
Tsinghua U.
14 years 13 days ago
OPTNET: A Cost-effective Optical Network for Multiprocessors
In this paper we propose the OPTNET, a novel optical network and associated coherence protocol for scalable multiprocessors. The network divides its channels into broadcast and po...
Enrique V. Carrera, Ricardo Bianchini
MICRO
1997
IEEE
128views Hardware» more  MICRO 1997»
14 years 12 days ago
Run-Time Spatial Locality Detection and Optimization
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...
Teresa L. Johnson, Matthew C. Merten, Wen-mei W. H...
SIGMOD
1997
ACM
135views Database» more  SIGMOD 1997»
14 years 12 days ago
High-Performance Sorting on Networks of Workstations
We report the performance of NOW-Sort, a collection of sorting implementations on a Network of Workstations (NOW). We find that parallel sorting on a NOW is competitive to sortin...
Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau,...
ISCA
1989
IEEE
109views Hardware» more  ISCA 1989»
14 years 7 days ago
Improving Performance of Small On-Chip Instruction Caches
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
Matthew K. Farrens, Andrew R. Pleszkun