3202 search results - page 457 / 641 » Memory access scheduling |
FDL
2004
IEEE
13 years 12 months ago
2004
IEEE
gn process of embedded systems moves currently towards higher levels of abstraction. As a consequence, a need arises for an early and realistic assessment of system level design d...
ATMOS
2008
13 years 9 months ago
2008
Abstract. The search for train connections in state-of-the-art commercial timetable information systems is based on a static schedule. Unfortunately, public transportation systems ...
JCST
2008
13 years 8 months ago
2008
The allocation of bandwidth to unlicensed users, without significantly increasing the interference on the existing licensed users, is a challenge for Ultra Wideband (UWB) networks....
IWOMP
2007
Springer
14 years 2 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
HPCC
2007
Springer
14 years 2 months ago
2007
Springer
To increase the scale and performance of scientific applications, scientists commonly distribute computation over multiple processors. Often without realizing it, file I/O is pa...