36 search results - page 3 / 8 » Memory bank aware dynamic loop scheduling |
ETFA
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents the incorporation of an auto-tuning real-time garbage collector into a feedback-based on-line scheduling system. The studied feedback scheduler is designed to ...
CSREAESA
2003
13 years 9 months ago
2003
− This paper presents an efficient system level power saving method for DRAM with multiple power modes. The proposed method is based on the power aware scheduling algorithm that ...
ISCAPDCS
2004
13 years 9 months ago
2004
Hyperthreaded(HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by ex...
JISE
2002
13 years 7 months ago
2002
Load balancing and data locality are the two most important factors in the performance of parallel programs on distributed-memory multiprocessors. A good balancing scheme should e...
SAMOS
2010
Springer
13 years 5 months ago
2010
Springer
A new heterogeneous multiprocessor system with dynamic memory and power management for improved performance and power consumption is presented. Increased data locality is automatic...