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» Merging Parallel Simulation Programs
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SPAA
2006
ACM
14 years 1 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ISHPC
1999
Springer
13 years 11 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
JPDC
2007
167views more  JPDC 2007»
13 years 7 months ago
On the design of high-performance algorithms for aligning multiple protein sequences on mesh-based multiprocessor architectures
In this paper, we address the problem of multiple sequence alignment (MSA) for handling very large number of proteins sequences on mesh-based multiprocessor architectures. As the ...
Diana H. P. Low, Bharadwaj Veeravalli, David A. Ba...
IEEEPACT
2008
IEEE
14 years 2 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
ESTIMEDIA
2007
Springer
14 years 1 months ago
Leveraging Predicated Execution for Multimedia Processing
—Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing processing requirements. Therefore, efficient solution...
Dietmar Ebner, Florian Brandner, Andreas Krall