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SAMOS
2007
Springer
15 years 10 months ago
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and
Abstract— This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have uniqu...
Francesco Regazzoni, Stéphane Badel, Thomas...
APCSAC
2006
IEEE
15 years 10 months ago
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
Lih Wen Koh, Oliver Diessel
ESERNET
2003
Springer
15 years 9 months ago
Functional Testing, Structural Testing, and Code Reading: What Fault Type Do They Each Detect?
The origin of the study described here is the experiment performed by Basili and Selby, further replicated by Kamsties and Lott, and once again by Wood et al. These experiments inv...
Natalia Juristo Juzgado, Sira Vegas
INFOCOM
2000
IEEE
15 years 8 months ago
End-to-End Congestion Control Schemes: Utility Functions, Random Losses and ECN Marks
We present a framework for designing end-to-end congestion control schemes in a network where each user may have a different utility function and may experience non-congestion-re...
Srisankar S. Kunniyur, Rayadurgam Srikant
DAC
2005
ACM
15 years 6 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...