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CSREAESA
2010
13 years 4 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
4OR
2005
104views more  4OR 2005»
13 years 6 months ago
The robust shortest path problem with interval data via Benders decomposition
Many real problems can be modelled as robust shortest path problems on digraphs with interval costs, where intervals represent uncertainty about real costs and a robust path is not...
Roberto Montemanni, Luca Maria Gambardella
SC
2005
ACM
14 years 9 days ago
Dynamic Data-Driven Inversion For Terascale Simulations: Real-Time Identification Of Airborne Contaminants
In contrast to traditional terascale simulations that have known, fixed data inputs, dynamic data-driven (DDD) applications are characterized by unknown data and informed by dynam...
Volkan Akcelik, George Biros, Andrei Draganescu, J...
FORMATS
2007
Springer
13 years 10 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson
DELTA
2004
IEEE
13 years 10 months ago
Static Scheduling of Monoprocessor Real-Time Systems composed of Hard and Soft Tasks
In this report we address the problem of static scheduling of realtime systems that include both hard and soft tasks. We consider systems in which both hard and soft tasks are per...
Luis Alejandro Cortés, Petru Eles, Zebo Pen...