109 search results - page 8 / 22 » Microcode Generation for Flexible Parallel Target Architectu... |
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
CDES
2006
13 years 8 months ago
2006
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
CG
2008
Springer
13 years 6 months ago
2008
Springer
Recent developments have produced several techniques for interactive ray tracing of dynamic scenes. In particular, bounding volume hierarchies (BVHs) are efficient acceleration st...
IPPS
2003
IEEE
13 years 12 months ago
2003
IEEE
To understand the performance of modern Java systems one must observe execution in the context of specific architectures. It is also important that we make these observations usi...
IPPS
2006
IEEE
14 years 22 days ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...