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FPL
2000
Springer
124views Hardware» more  FPL 2000»
15 years 7 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
GRAPHICSINTERFACE
2007
15 years 5 months ago
Optimized subdivisions for preprocessed visibility
This paper describes a new tool for preprocessed visibility. It puts together view space and object space partitioning in order to control the render cost and memory cost of the v...
Oliver Mattausch, Jirí Bittner, Peter Wonka...
PDPTA
2007
15 years 5 months ago
Scheduling Divisible Workloads from Multiple Sources in Linear Daisy Chain Networks
— This paper considers scheduling divisible workloads from multiple sources in linear networks of processors. We propose a two phase scheduling strategy (TPSS) to minimize the ov...
Xinxin Liu, Han Zhao, Xiaolin Li
IJCAI
2001
15 years 5 months ago
Symbolic Dynamic Programming for First-Order MDPs
We present a dynamic programming approach for the solution of first-order Markov decisions processes. This technique uses an MDP whose dynamics is represented in a variant of the ...
Craig Boutilier, Raymond Reiter, Bob Price
IJCAI
1993
15 years 5 months ago
Multi-Interval Discretization of Continuous-Valued Attributes for Classification Learning
Since most real-world applications of classification learning involve continuous-valued attributes, properly addressing the discretization process is an important problem. This pa...
Usama M. Fayyad, Keki B. Irani