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HPCA
2003
IEEE
14 years 10 months ago
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
Li Shang, Li-Shiuan Peh, Niraj K. Jha
ICCD
2006
IEEE
77views Hardware» more  ICCD 2006»
14 years 7 months ago
Iterative-Constructive Standard Cell Placer for High Speed and Low Power
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
Sungjae Kim, Eugene Shragowitz
ICCD
2006
IEEE
124views Hardware» more  ICCD 2006»
14 years 7 months ago
Customizable Fault Tolerant Caches for Embedded Processors
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
Subramanian Ramaswamy, Sudhakar Yalamanchili
ICCAD
2008
IEEE
89views Hardware» more  ICCAD 2008»
14 years 7 months ago
Temperature aware task sequencing and voltage scaling
Abstract—On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of syst...
Ramkumar Jayaseelan, Tulika Mitra
ICCAD
2007
IEEE
131views Hardware» more  ICCAD 2007»
14 years 7 months ago
Low-overhead design technique for calibration of maximum frequency at multiple operating points
— Determination of maximum operating frequencies (Fmax) during manufacturing test at different operating voltages is required to: (a) to ensure that, for a Dynamic Voltage and Fr...
Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid...