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» Minimizing power across multiple technology and design level...
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JETC
2008
127views more  JETC 2008»
13 years 6 months ago
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
Yong Zhan, Sachin S. Sapatnekar
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Logic and Layout Aware Voltage Island Generation for Low Power Design
Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but...
Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
DAC
2003
ACM
14 years 8 months ago
Pushing ASIC performance in a power envelope
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kun...
ICCAD
2004
IEEE
118views Hardware» more  ICCAD 2004»
14 years 4 months ago
Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization
New embedded systems offer rich power management features in the form of multiple operational and non-operational power modes. While they offer mechanisms for better energy effic...
Jinfeng Liu, Pai H. Chou
TMM
2011
121views more  TMM 2011»
13 years 2 months ago
Spread Spectrum Visual Sensor Network Resource Management Using an End-to-End Cross-Layer Design
—In this paper, we propose an approach to manage network resources for a direct sequence code division multiple access (DS-CDMA) visual sensor network where nodes monitor scenes ...
Elizabeth S. Bentley, Lisimachos P. Kondi, John D....