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ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
13 years 11 months ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
CASES
2001
ACM
13 years 11 months ago
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
Girish Venkataramani, Walid A. Najjar, Fadi J. Kur...
CCGRID
2001
IEEE
13 years 11 months ago
Replica Selection in the Globus Data Grid
The Globus Data Grid architecture provides a scalable infrastructure for the management of storage resources and data that are distributed across Grid environments. These services...
Sudharshan Vazhkudai, Steven Tuecke, Ian T. Foster
SIGCOMM
2000
ACM
13 years 11 months ago
Memory-efficient state lookups with fast updates
Routers must do a best matching pre x lookup for every packet solutions for Gigabit speeds are well known. As Internet link speeds higher, we seek a scalable solution whose speed ...
Sandeep Sikka, George Varghese
SIGGRAPH
1995
ACM
13 years 11 months ago
Creation and rendering of realistic trees
Recent advances in computer graphics have produced images approaching the elusive goal of photorealism. Since many natural objects are so complex and detailed, they are often not ...
Jason Weber, Joseph Penn