1222 search results - page 123 / 245 » Mistreatment-resilient distributed caching |
HPCA
2000
IEEE
14 years 1 months ago
2000
IEEE
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
In order to reduce the overhead of synchronizing operations of shared memory multiprocessors, this paper proposes a mechanism, named specMEM, to execute memory accesses following ...
HPCA
1999
IEEE
14 years 1 months ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
HPCA
1999
IEEE
14 years 1 months ago
1999
IEEE
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
IEEEPACT
1999
IEEE
14 years 1 months ago
1999
IEEE
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...