Sciweavers

262 search results - page 23 / 53
» Mnemosyne: Designing and Implementing Network Short-Term Mem...
Sort
View
DSN
2003
IEEE
14 years 1 months ago
On the Design of Robust Integrators for Fail-Bounded Control Systems
This paper describes the design and evaluation of a robust integrator for software-implemented control systems. The integrator is constructed as a generic component in the Simulin...
Jonny Vinter, Andréas Johansson, Peter Folk...
IEEEPACT
2008
IEEE
14 years 2 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
CN
2000
126views more  CN 2000»
13 years 8 months ago
Cartesian routing
The dominant backbone protocol implemented in the Internet is the Border Gateway Protocol (BGP). Each router implementing BGP maintains a routing table. As networks increase in si...
Larry Hughes, Omid Banyasad, Evan J. Hughes
IMC
2010
ACM
13 years 6 months ago
High speed network traffic analysis with commodity multi-core systems
Multi-core systems are the current dominant trend in computer processors. However, kernel network layers often do not fully exploit multi-core architectures. This is due to issues...
Francesco Fusco, Luca Deri
PVLDB
2011
12 years 11 months ago
Merging What's Cracked, Cracking What's Merged: Adaptive Indexing in Main-Memory Column-Stores
Adaptive indexing is characterized by the partial creation and refinement of the index as side effects of query execution. Dynamic or shifting workloads may benefit from prelimi...
Stratos Idreos, Stefan Manegold, Harumi A. Kuno, G...