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QEST
2007
IEEE
14 years 1 months ago
Performance Trees: Expressiveness and Quantitative Semantics
—Performance Trees are a recently-proposed mechanism for the specification of performance properties and measures. They represent an attractive alternative to stochastic logics,...
Tamas Suto, Jeremy T. Bradley, William J. Knottenb...
CAV
2000
Springer
187views Hardware» more  CAV 2000»
13 years 11 months ago
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
In this paper we show how to do symbolic model checking using Boolean Expression Diagrams (BEDs), a non-canonical representation for Boolean formulas, instead of Binary Decision Di...
Poul Frederick Williams, Armin Biere, Edmund M. Cl...
FMCAD
2008
Springer
13 years 9 months ago
Automatic Non-Interference Lemmas for Parameterized Model Checking
Parameterized model checking refers to any method that extends traditional, finite-state model checking to handle systems arbitrary number of processes. One popular approach to thi...
Jesse D. Bingham
MEMOCODE
2005
IEEE
14 years 1 months ago
Three-valued logic in bounded model checking
In principle, bounded model checking (BMC) leads to semidecision procedures that can be used to verify liveness properties and to falsify safety properties. If the procedures fail...
Tobias Schüle, Klaus Schneider
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
14 years 23 days ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee