2661 search results - page 36 / 533 » Model Checking Performability Properties |
ISVLSI
2007
IEEE
14 years 3 months ago
2007
IEEE
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
CORR
2008
Springer
13 years 8 months ago
2008
Springer
Abstract. This paper presents a novel technique for counterexample generation in probabilistic model checking of Markov chains and Markov Decision Processes. (Finite) paths in coun...
APN
2000
Springer
14 years 1 months ago
2000
Springer
One of the most efficient analysis technique is to reduce an original model into a simpler one such that the reduced model has the same properties than the original one. G. Berthel...
ICECCS
2007
IEEE
14 years 3 months ago
2007
IEEE
In this paper we summarize parallel algorithms for enumerative model checking of properties formulated in linear time temporal logic (LTL) as well as a fragment of the µcalculus ...
ATVA
2006
Springer
14 years 14 days ago
2006
Springer
In the past decades, many formal frameworks (e.g. timed automata and temporal logics) and techniques (e.g. model checking and theorem proving) have been proposed to model a real-ti...