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FORTE
2004
14 years 10 days ago
Witness and Counterexample Automata for ACTL
Witnesses and counterexamples produced by model checkers provide a very useful source of diagnostic information. They are usually returned in the form of a single computation path ...
Robert Meolic, Alessandro Fantechi, Stefania Gnesi
HYBRID
2010
Springer
14 years 5 months ago
On the connections between PCTL and dynamic programming
Probabilistic Computation Tree Logic (PCTL) is a wellknown modal logic which has become a standard for expressing temporal properties of finite-state Markov chains in the context...
Federico Ramponi, Debasish Chatterjee, Sean Summer...
RTA
2000
Springer
14 years 2 months ago
Parallelism Constraints
Parallelism constraints are logical descriptions of trees. Parallelism constraints subsume dominance constraints and are equal in expressive power to context unification. Paralleli...
Katrin Erk, Joachim Niehren
GLVLSI
2009
IEEE
150views VLSI» more  GLVLSI 2009»
14 years 5 months ago
Contradictory antecedent debugging in bounded model checking
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
Daniel Große, Robert Wille, Ulrich Kühn...
CONCUR
2007
Springer
14 years 2 months ago
Temporal Antecedent Failure: Refining Vacuity
We re-examine vacuity in temporal logic model checking. We note two disturbing phenomena in recent results in this area. The first indicates that not all vacuities detected in prac...
Shoham Ben-David, Dana Fisman, Sitvanit Ruah