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ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
IFIP
2001
Springer
13 years 12 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
VTS
1997
IEEE
105views Hardware» more  VTS 1997»
13 years 11 months ago
Critical hazard free test generation for asynchronous circuits
We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropos...
Ajay Khoche, Erik Brunvand
ATS
1998
IEEE
106views Hardware» more  ATS 1998»
13 years 11 months ago
A Test Pattern Generation Algorithm Exploiting Behavioral Information
This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level The main problem of using behavioral information for ATPG is the mismatch of timing models bet...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
HT
2004
ACM
14 years 29 days ago
Automatic generation of hypertext system repositories: a model driven approach
In this paper, we present a model-driven methodology and toolset for automatic generation of hypertext system repositories. Our code generator, called Bamboo, is based on a Contai...
E. James Whitehead Jr., Guozheng Ge, Kai Pan