Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropos...
This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level The main problem of using behavioral information for ATPG is the mismatch of timing models bet...
In this paper, we present a model-driven methodology and toolset for automatic generation of hypertext system repositories. Our code generator, called Bamboo, is based on a Contai...