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» Model checking SystemC designs using timed automata
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ECBS
2007
IEEE
145views Hardware» more  ECBS 2007»
13 years 10 months ago
Automatic Verification and Performance Analysis of Time-Constrained SysML Activity Diagrams
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...
SCP
2010
155views more  SCP 2010»
13 years 5 months ago
Type inference and strong static type checking for Promela
The SPIN model checker and its specification language Promela have been used extensively in industry and academia to check logical properties of distributed algorithms and protoc...
Alastair F. Donaldson, Simon J. Gay
ARTS
1997
Springer
13 years 10 months ago
The Verus Language: Representing Time Efficiently with BDDs
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
Sérgio Vale Aguiar Campos, Edmund M. Clarke
EMSOFT
2006
Springer
13 years 10 months ago
Modeling a system controller for timing analysis
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
Stephan Thesing
ECMDAFA
2005
Springer
236views Hardware» more  ECMDAFA 2005»
14 years 9 days ago
Model-Driven Architecture for Hard Real-Time Systems: From Platform Independent Models to Code
The model-driven software development for hard real-time systems promotes the usage of the platform independent model as major design artifact. It is used to develop the software l...
Sven Burmester, Holger Giese, Wilhelm Schäfer