880 search results - page 27 / 176 » Model checking erlang programs: the functional approach |
166
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CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
122
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ISVLSI
2007
IEEE
15 years 11 months ago
2007
IEEE
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
123
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FSEN
2007
Springer
15 years 8 months ago
2007
Springer
Abstract. We present Trio2Promela, a tool for model checking TRIO specifications by means of Spin. TRIO is a linear-time temporal logic with both future and past operators and a qu...
152
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ICRE
1998
IEEE
15 years 9 months ago
1998
IEEE
Model checking is shown to be an effective tool in validating the behavior of a fault tolerant embedded spacecraft controller. The case study presented here at by judiciously abst...
148
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IFM
2009
Springer
15 years 11 months ago
2009
Springer
We present the new technique of dynamic path reduction (DPR), which allows one to prune redundant paths from the state space of a program under verification. DPR is a very general...