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LPAR
2005
Springer
14 years 2 months ago
Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination
Separation logic is a subset of the quantifier-free first order logic. It has been successfully used in the automated verification of systems that have large (or unbounded) inte...
Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti G...
CEC
2008
IEEE
14 years 3 months ago
Finding liveness errors with ACO
Abstract— Model Checking is a well-known and fully automatic technique for checking software properties, usually given as temporal logic formulae on the program variables. Most o...
J. Francisco Chicano, Enrique Alba
POPL
2002
ACM
14 years 9 months ago
Predicate abstraction for software verification
e Abstraction for Software Verification Cormac Flanagan Shaz Qadeer Compaq Systems Research Center 130 Lytton Ave, Palo Alto, CA 94301 Software verification is an important and di...
Cormac Flanagan, Shaz Qadeer
CAV
2007
Springer
122views Hardware» more  CAV 2007»
14 years 25 days ago
Parameterized Verification of Infinite-State Processes with Global Conditions
We present a simple and effective approximated backward reachability algorithm for parameterized systems with existentially and universally quantified global conditions. The indivi...
Parosh Aziz Abdulla, Giorgio Delzanno, Ahmed Rezin...
ICSE
2000
IEEE-ACM
14 years 12 days ago
Verification of time partitioning in the DEOS scheduler kernel
This paper describes an experiment to use the Spin model checking system to support automated verification of time partitioning in the Honeywell DEOS real-time scheduling kernel. ...
John Penix, Willem Visser, Eric Engstrom, Aaron La...