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ESTIMEDIA
2004
Springer
14 years 2 months ago
A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...
Tien-Wei Hsieh, Youn-Long Lin
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
14 years 23 days ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
CP
1998
Springer
14 years 1 months ago
Modelling CSP Solution Algorithms with Petri Decision Nets
The constraint paradigm provides powerful concepts to represent and solve different kinds of planning problems, e. g. factory scheduling. Factory scheduling is a demanding optimiz...
Stephan Pontow
IACR
2011
252views more  IACR 2011»
12 years 9 months ago
A Meet-in-the-Middle Attack on the Full KASUMI
KASUMI is a block cipher which consists eight Feistel rounds with a 128-bit key. The confidentiality and integrity of UMTS, GSM and GPRS mobile communications systems depend heavi...
Keting Jia, Hongbo Yu, Xiaoyun Wang
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 9 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...