356 search results - page 48 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
ITNG
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
HPCC
2009
Springer
14 years 1 months ago
2009
Springer
—In this paper we present C2Cfs - a decentralized collective caching architecture for distributed filesystems. C2Cfs diverges from the traditional client-server model and advoca...
GLVLSI
2011
IEEE
13 years 12 days ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
HPCA
1997
IEEE
14 years 27 days ago
1997
IEEE
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
ICPP
1998
IEEE
14 years 28 days ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...