2805 search results - page 122 / 561 » Modeling Memory for Melodies |
138
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IPPS
2010
IEEE
15 years 2 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
129
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
119
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DSD
2004
IEEE
15 years 8 months ago
2004
IEEE
Tile-based rendering (also called chunk rendering or bucket rendering) is a promising technique for low-power, 3D graphics platforms. This technique decomposes a scene into smalle...
177
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IPPS
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications’ p...
103
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
— Compared with a single level Hamming associative memory, a simple model based on uniform random noise analysis has proved a twolevel decoupled Hamming network to be an efficie...