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CGO
2009
IEEE
14 years 4 months ago
Reducing Memory Ordering Overheads in Software Transactional Memory
—Most research into high-performance software transactional memory (STM) assumes that transactions will run on a processor with a relatively strict memory model, such as Total St...
Michael F. Spear, Maged M. Michael, Michael L. Sco...
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
14 years 1 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
CAV
2006
Springer
165views Hardware» more  CAV 2006»
14 years 1 months ago
Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study
Many multithreaded programs employ concurrent data types to safely share data among threads. However, highly-concurrent algorithms for even seemingly simple data types are difficul...
Sebastian Burckhardt, Rajeev Alur, Milo M. K. Mart...
QSIC
2008
IEEE
14 years 4 months ago
Path and Context Sensitive Inter-procedural Memory Leak Detection
This paper presents a practical path and context sensitive inter-procedural analysis method for detecting memory leaks in C programs. A novel memory object model and function summ...
Zhongxing Xu, Jian Zhang
CAV
2004
Springer
97views Hardware» more  CAV 2004»
14 years 3 months ago
Efficient Modeling of Embedded Memories in Bounded Model Checking
Malay K. Ganai, Aarti Gupta, Pranav Ashar