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UML
2004
Springer
14 years 2 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
TII
2008
98views more  TII 2008»
13 years 9 months ago
Formal Methods for Systems Engineering Behavior Models
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...
Charlotte Seidner, Olivier H. Roux
SIGSOFT
2005
ACM
14 years 9 months ago
Towards a unified formal model for supporting mechanisms of dynamic component update
The continuous requirements of evolving a delivered software system and the rising cost of shutting down a running software system are forcing researchers and practitioners to fin...
Junrong Shen, Xi Sun, Gang Huang, Wenpin Jiao, Yan...
IFM
2009
Springer
155views Formal Methods» more  IFM 2009»
13 years 6 months ago
Application of Graph Transformation in Verification of Dynamic Systems
Abstract. A communication system evolves dynamically with the addition and deletion of services. In our previous work [12], a graph transformation system (GTS) was used to model th...
Zarrin Langari, Richard J. Trefler
KBSE
2005
IEEE
14 years 2 months ago
A threat-driven approach to modeling and verifying secure software
This paper presents a formal approach to threat-driven modeling and verification of secure software using aspect-oriented Petri nets. Based on the behavior model of intended funct...
Dianxiang Xu, Kendall E. Nygard