458 search results - page 4 / 92 » Modeling and Formal Verification of DHCP Using SPIN |
ATVA
2007
Springer
13 years 11 months ago
2007
Springer
We present a new verification technique for Promela which exploits state-space symmetries induced by scalarset values used in a model. The technique involves efficiently computing ...
SPIN
2004
Springer
14 years 29 days ago
2004
Springer
Abstract. In the classic approach to logic model checking, software verification requires a manually constructed artifact (the model) to be written in the language that is accepted...
APSEC
2005
IEEE
14 years 1 months ago
2005
IEEE
The lack of a precise semantics for UML activity diagrams makes the reasoning on models constructed using such diagrams infeasible. However, such diagrams are widely used in domai...
COMPSAC
2003
IEEE
14 years 27 days ago
2003
IEEE
RDT is a graphical formal modelling language in which the modeller works by constructing diagrams of the processes in their model which they then join together to form complete sy...
FMCAD
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. In this paper we describe the formal specification and verification of the efficient algorithm for real-time model checking implemented in the model checker RAVEN. It was...