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» Modeling and Formal Verification of DHCP Using SPIN
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SPIN
2000
Springer
13 years 11 months ago
The Temporal Rover and the ATG Rover
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
Doron Drusinsky
JSA
2008
131views more  JSA 2008»
13 years 7 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...
FMICS
2010
Springer
13 years 8 months ago
A Formal Model of Identity Mixer
Identity Mixer is an anonymous credential system developed at IBM that allows users for instance to prove that they are over 18 years old without revealing their name or birthdate....
Jan Camenisch, Sebastian Mödersheim, Dieter S...
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
14 years 27 days ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
CAV
1997
Springer
102views Hardware» more  CAV 1997»
13 years 11 months ago
Efficient Model Checking Using Tabled Resolution
We demonstrate the feasibility of using the XSB tabled logic programming system as a programmable fixed-point engine for implementing efficient local model checkers. In particular,...
Y. S. Ramakrishna, C. R. Ramakrishnan, I. V. Ramak...