We propose a format of predicate diagrams for the verification of real-time systems. We consider systems that are defined as extended timed graphs, a format that combines timed au...
In this paper we argue the case for integrating the distinctive functionalities of logic programs and production systems within an abductive logic programming agent framework. In t...
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
Ensuring that the content of a rule-base, which is being encoded, is free from problems of consistency, completeness, and conciseness, is necessary to avoid any performance errors...
The search for proof and the search for counterexamples (bugs) are complementary activities that need to be pursued concurrently in order to maximize the practical success rate of...
Ashutosh Gupta, Thomas A. Henzinger, Rupak Majumda...