222 search results - page 40 / 45 » Modeling transactional memory workload performance |
ISCA
1997
IEEE
14 years 23 days ago
1997
IEEE
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
DASFAA
2009
IEEE
13 years 12 months ago
2009
IEEE
Abstract. Fine-grained lock protocols with lock modes and lock granules adjusted to the various XML processing models, allow for highly concurrent transaction processing on XML tre...
POPL
2006
ACM
14 years 8 months ago
2006
ACM
The movement to multi-core processors increases the need for simpler, more robust parallel programming models. Atomic sections have been widely recognized for their ease of use. T...
WSC
1997
13 years 10 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
OSDI
2008
ACM
14 years 8 months ago
2008
ACM
Deadlock is an increasingly pressing concern as the multicore revolution forces parallel programming upon the average programmer. Existing approaches to deadlock impose onerous bu...