Sciweavers

222 search results - page 41 / 45
» Modeling transactional memory workload performance
Sort
View
PADS
1999
ACM
14 years 26 days ago
Shock Resistant Time Warp
In an attempt to cope with time-varying workload, traditional adaptive Time Warp protocols are designed to react in response to performance changes by altering control parameter c...
Alois Ferscha, James Johnson
OOPSLA
2010
Springer
13 years 7 months ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek
LCTRTS
2010
Springer
14 years 3 months ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski
WWW
2005
ACM
14 years 9 months ago
A multi-threaded PIPELINED Web server architecture for SMP/SoC machines
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. D...
C3S2E
2009
ACM
14 years 17 days ago
The promise of solid state disks: increasing efficiency and reducing cost of DBMS processing
Most database systems (DBMSs) today are operating on servers equipped with magnetic disks. In our contribution, we want to motivate the use of two emerging and striking technologi...
Karsten Schmidt 0002, Yi Ou, Theo Härder